Charge coupled devices (CCDs) are used in a large variety of digital imaging applications. There are a number of different manufacturers of such devices and each manufacturer typically has numerous models. The large variety of CCDs and the continuously evolving CCD control requirements have caused challenges in designing the analog front end/CCD controller circuits that will have significant longevity in the market place. This problem is ameliorated to a large extent by the software programmable pattern generator described in the '000 and '449 applications, incorporated by reference above. That software programmable pattern generator utilizes a compact and flexible assembly programmable Reduced Instruction Set Computer (RISC) that is optimized for generating high precision timing pulses and low power control functions. The architecture has a variable bit wide instruction set that includes: vector toggling instructions, jump instructions, conditional instructions, arithmetic instructions, and load/store instructions. The pattern generator can fetch and execute one instruction per clock cycle, and is parameter scalable to allow for easy optimization in different applications.
To allow every chip output to be set simultaneously at a pixel clock resolution, a large number of bits may be stored in parallel within the program memory, with each bit in a vector word corresponding to an output pin that can be selectively toggled, depending on the state of the bit. In the case of Analog Device's model number ADDI9000, this meant that every instruction was “64” bits wide. An advantage of this model was in the simple control and design logic required. We have since recognized, however, that the use of such large instructions consumes a significant amount of memory, thus imposing limits on the utility of the timing generator for certain applications.